The present invention relates generally to integrated circuits and, more particularly, to a fractional frequency divider suitable for performing division of a digital clock or timing signal.
Fractional frequency dividers typically perform division by a fraction m/n where a divided signal has ‘m’ pulses for every ‘n’ pulses of an original signal (where ‘m’ and ‘n’ are integers and ‘m’ is less than ‘n’), thus allowing a digital waveform to be divided by non-integer values.
In one known fractional frequency divider, an integer divider performs a frequency division based on a variable divisor that is controlled by a Delta Sigma modulator. One problem with known fractional frequency dividers is the problem of overrun and underrun due to an uncontrolled duty cycle. A configurable duty cycle is particularly advantageous in NAND Flash Controller applications where a divided output clock having a duty cycle to match the requirements of its associated Flash memory unit is required. A further problem with known arrangements is jitter, which is the unwanted variation of the divided clock period over time.
It would be advantageous to provide a fractional frequency divider that mitigates the drawbacks of the known arrangements.